y Acceptable input signal voltages ranges from 0 to 0.8 volts for low logic state and 2 to 5 Volts for high logic state.ĭOS Be regular to the lab Follow proper dress codeĭONTS Do not exceed the voltage rating Do not interchange the ICs while doing the experiment Avoid loose connections and short circuits y However real TTL gates cannot output such perfect voltage levels and are designed to accept high and low signals deviating substantially from these ideal values. Ideally a TTL high signal would be 5V exactly and TTL low signal 0.0V exactly. LOGIC SIGNAL VOLTAGE LEVELS: y TTL gates operate on a nominal power supply voltage of 5V, +/- 2.5V.
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In the figure, the stated function is certainly true (switch open), and this does correspond to a high voltage at the labeled point.
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The labeled voltage is High (Low) when the labels stated function is True (False). The convention for naming these states is illustrated in Fig. y In the case of the TTL logic gates we will be using in the lab, the Low voltage state is roughly 0-1 Volt and the High state is roughly 2:5-5 Volts. So in practice, the terms digital and binary are used interchangeably.īINARY LOGIC STATES: y The following table attempts to make correspondences between conventions for defining binary logic states. Hence, the digital information is intrinsically binary. This circuitry is based upon the transistor, which can be operated as a switch with two states. The explosion in digital techniques and technology has been made possible by the incredible increase in the density of digital circuitry, its robust performance, its relatively low cost, and its speed. y To study about FPGAs and synthesis tools.īASICS: y Some information is intrinsically digital, so it is natural to process and manipulate it using purely digital techniques. Represent hierarchical combinational logic systems by interconnecting instances of other modules. Understand the requirements of input and output signals in a Verilog module. To Design multiple bit adders, Subtractors & multipliers Analyze and Implement an Master/Slave Flip-Flop, D Flip-Flop, T Flip-Flop To study and design counters & shift registers Understand the Verilog module as a hierarchical construct for describing logic circuits. To Implement a circuit from a truth-table or logic function To Understand the function, purpose, and representation of a multiplexer To Design a simple circuit logic circuit using logic gates and multiplexers. OBJECTIVES: y y y y y y y y y y To understand how logic expressions express an output as a function of various inputs. Design of mono-shots using dedicated ICs (74123). Design of astable & mono-stable multi-vibrators using gates. Introduction to CAD and VERILOG HDL HANDOUT PROBLEMS: 1. Study of counter ICs (7490, 74190).DIGITAL IC LAB | Karthik.SĢ. Multiplexer & demultiplexer using VERILOG.
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Design of 7 segment display circuits-static/dynamic (7447, FND542). Counters using shift registers (Ring counter & Johnson counter). Design and testing of ripple & synchronous counters using JK flip flops (7473, 7476) 7.
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Adders, Subtractors & Multipliers (Barrel shifter).
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Design of half adder & full adder using gates. Logic family interconnection (TTL to CMOS & CMOS to TTL) 4. Interfacing of TTL & electromagnetic relay using transistor, opto-coupler (4N33) & Darlington arrays (ULN2803). TTL & CMOS characteristics (7400, CD4001) 2. ASHA P.SĭIGITAL IC LABMANUALLIST OF EXPERIMENTS: CYCLE: I 1. ECE 5TH SEMESTER- SNGCE Karthik.S Authored by: 1.